Title of Paper:A new hierarchical genetic algorithm for low-power network on chip design

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Date of Publication:2010-01-01

Included Journals:EI、Scopus

Issue:PART 2

Page Number:159-162

Abstract:A new hierarchical genetic algorithm for low-power network on chip (NoC) design is proposed in this paper. As 2D-mesh is a widely used NoC topology, this paper studies the optimization of mapping IP (intellectual property) cores onto regular and irregular 2D-mesh network while minimizing communication power consumption. Experimental results show that significant energy savings can be achieved. For instance, for a given application, up to 39% energy savings have been observed. ? 2010 IEEE.