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论文类型：会议论文

第一作者：Cai, Jian

合写作者：Wang, Qian,Wang, Dejun,Wang, Junqiang,Wu, Zijian

发表时间：2017-01-01

收录刊物：SCIE、Scopus、EI、CPCI-S

卷号：0

页面范围：1742-1747

关键字：3D integration; solid-state-diffusion (SSD); bonding; surface pretreatment; electromigration (EM)

摘要：In this work, current stress was applied to investigate electromigration (EM) effects for Cu/Sn/Cu solid-state-diffusion (SSD) bonding in 3D integration. Full-array bumps with different pitches were fabricated on wafers. Asymmetric structure of Cu/Sn bump and Cu bump was deposited by low-cost electroplating process. With optimized surface pretreatment, wafer-level Cu/Sn/Cu SSD bonding was performed at a low temperature of 200 degrees C for 30 min under a vacuum of 10(-5) mbar. As-bonded wafers were annealed at 200 degrees C for 60 min under N-2 atmosphere and then diced into dies. The bonding interface consisted of Cu/Cu3Sn/Cu6Sn5/Cu3Sn/Cu, without pure Sn remained and Sn overflow. After further annealing process for bonded dies, the middle layer of Cu6Sn5 has been completely exhausted, and the interface transformed to Cu/Cu3Sn/Cu. The bonding strength has reached above 70 MPa. Subsequently, the three-layer structure was subjected to EM test at 150 degrees C for 500 hours with current density of 2.0x10(4) A/cm(2). No void or crack caused by atom migration appeared at the cathode and the anode. Bonding strength also kept at above 70 MPa, and no electrical degeneration occurred according to resistance measurement. It is concluded that high-quality Cu/Sn/Cu bonding was realized using SSD technology and exhibited an expected anti-electromigration capability.