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BCH码译码器的FPGA实现
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Indexed by:期刊论文

Date of Publication:2000-12-30

Journal:电路与系统学报

Included Journals:CSCD

Volume:5

Issue:4

Page Number:98-100

ISSN No.:1007-0249

Key Words:BCH码;译码;FPGA

Abstract:在通信领域,差错控制技术能有效地改善通信系统的传输性能.作者在本文中探讨了BCH码的译码算法,并用Altera FPGA实现了BCH(31,21)码的两种硬件译码.一种是串行译码;另一种是并行译码.取得了令人满意的结果.

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Gender:Female

Alma Mater:大连理工大学

Degree:Doctoral Degree

School/Department:信息与通信工程学院

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