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Indexed by:会议论文

Date of Publication:2011-12-01

Included Journals:EI、Scopus

Volume:136 LNEE

Page Number:377-384

Abstract:In this paper, we presents a novel method towards PSL assertion checking by using computer algebra system to perform symbolic simulation over synchronous circuit model. The method we studied is based on Groebner bases and can deal with a constrained subset of PSL Boolean layer. We provide an algorithm framework based on constructing data-flow model and calculating the zero set relationship of their polynomials. This paper shows that computer algebra can provide canonical symbolic representations for assertions as well as circuit system models. The approach to symbolic simulation will be a useful supplement to the existent verification methods based on simulation. ? 2012 Springer-Verlag.