Kaiyu Wang
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Verilog HDL optimisation design and simulation for modified inversionless Berlerkamp-Massey algorithm and the multiplier over canonical field
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Indexed by:期刊论文

Date of Publication:2013-01-01

Journal:International Journal of Mobile Network Design and Innovation

Included Journals:EI、Scopus

Volume:5

Issue:1

Page Number:51-62

ISSN No.:17442869

Abstract:Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital transmission data against errors. This paper adopts the excellent inversionless Berlerkamp-Massey (IBM) algorithm as solving key equation algorithm for RS (204, 188) and then further modifies it to implement in less hardware resources after comparison with existing other algorithms. After that, we analyse critical path delay of the modified algorithm implemented in hardware and conclude that the multiplier over canonical field dominates a main part of the delay. Therefore, an efficient combinatorial multiplier of 4-input look up table (4-LUT) field programmable logic gate array (FPGA) is designed and then applied to the modified IBM algorithm. Results show that the modified IBM algorithm can be implemented using easier hardware structure, but when the proposed multiplier is applied to the modified IBM algorithm, in comparison with the two multipliers directly represented by a normal basis and matrix form, the speed to solve key equation increases by 10.2% and 18.4%, respectively. Copyright ? 2013 Inderscience Enterprises Ltd.

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教授级高工
Supervisor of Master's Candidates

Main positions:控制科学与工程学院副院长

Other Post:大连理工大学电工电子国家级实验教学示范中心主任,大连理工大学电工电子国家级虚拟仿真实验教学中心主任

Gender:Male

Alma Mater:德国卡尔斯普厄科技大学

Degree:Master's Degree

School/Department:控制科学与工程学院

Discipline:Detection Technology and Automation Device

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