Kaiyu Wang
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Paper Publications
FPGA-based implementation of all-digital QPSK carrier recovery loop combining costas loop and maximum likelihood frequency estimator
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Indexed by:期刊论文

Date of Publication:2014-01-01

Journal:International Journal of Reconfigurable Computing

Included Journals:EI、Scopus

Volume:2014

ISSN No.:16877195

Abstract:This paper presents an efficient all digital carrier recovery loop (ADCRL) for quadrature phase shift keying (QPSK). The ADCRL combines classic closed-loop carrier recovery circuit, all digital Costas loop (ADCOL), with frequency feedward loop, maximum likelihood frequency estimator (MLFE) so as to make the best use of the advantages of the two types of carrier recovery loops and obtain a more robust performance in the procedure of carrier recovery. Besides, considering that, for MLFE, the accurate estimation of frequency offset is associated with the linear characteristic of its frequency discriminator (FD), the Coordinate Rotation Digital Computer (CORDIC) algorithm is introduced into the FD based on MLFE to unwrap linearly phase difference. The frequency offset contained within the phase difference unwrapped is estimated by the MLFE implemented just using some shifter and multiply-accumulate units to assist the ADCOL to lock quickly and precisely. The joint simulation results of ModelSim and MATLAB show that the performances of the proposed ADCRL in locked-in time and range are superior to those of the ADCOL. On the other hand, a systematic design procedure based on FPGA for the proposed ADCRL is also presented. ? 2014 Kaiyu Wang et al.

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教授级高工
Supervisor of Master's Candidates

Main positions:控制科学与工程学院副院长

Other Post:大连理工大学电工电子国家级实验教学示范中心主任,大连理工大学电工电子国家级虚拟仿真实验教学中心主任

Gender:Male

Alma Mater:德国卡尔斯普厄科技大学

Degree:Master's Degree

School/Department:控制科学与工程学院

Discipline:Detection Technology and Automation Device

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