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A new WCET estimation algorithm besed on instruction cache and prefetching combined model

Release Time:2019-03-11  Hits:

Indexed by: Conference Paper

Date of Publication: 2004-12-09

Included Journals: EI

Volume: 3605 LNCS

Page Number: 557-562

Abstract: It is necessary to compute the execution time upper bound of embedded hard real-time program under the worst condition in embedded system design, which decides how hardware and software to partition and how to schedule process. Modern microprocessor which uses instruction cache memory and instruction pre-fetching increases the difficulty to compute the upper bound accurately. A new estimation method of embedded software performance based on instruction cache and pre-fetching model is proposed, which uses control flow graph and cache conflict graph and combine instruction pre-fetching into instruction cache analysis. It makes the execution time upper bound estimation under worst condition more accurate. © Springer-Verlag Berlin Heidelberg 2005.

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