LUT-DSP usage trade-off for re-configurable convolution acceleration core based on small logarithmic floating point representation
Release Time:2024-08-05 Hits:
Indexed by: Journal Papers
Document Code: 383147
Date of Publication: 2024-04-18
Journal: INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
Volume: 52
Issue: 4
Page Number: 1864-1871
ISSN: 0098-9886
Key Words: FPGA