Current position: Home >> Scientific Research >> Patents

一种面向Verilog HDL设计的故障注入方法

Hits:

First Author:Wang Jie

Disigner of the Invention:柳继伟,陈伟浩,李浩然,石霖

Affilication of Author(s):软件学院

Application Number:CN105302547A

Authorization number:CN201510599306.8

Pre One:基于FPGA期货套利实时分析系统V1.0

Next One:基于XML中间模型以及缺陷模式匹配的静态检测系统
Recommended Ph.D.Supervisor Recommended MA Supervisor Institutional Repository Personal Page

Address: No.2 Linggong Road, Ganjingzi District, Dalian City, Liaoning Province, P.R.C., 116024

Click : times
  • MOBILE Version
    •
    Open time:..
    The Last Update Time:..

    Mobile phone sweep