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论文类型：期刊论文

发表时间：2012-03-01

发表刊物：Journal of Convergence Information Technology

收录刊物：EI、Scopus

卷号：7

期号：4

页面范围：271-279

ISSN号：19759320

摘要：In symbolic computation area, Wu's method is an efficient way to solve algebraic equations, and has succeeded in geometry theorem proving. In this paper, we propose a technique solution towards PSL assertion checking by applying Wu's method to symbolic simulation over synchronous circuit model. A mechanism for constructing polynomial representations of circuit descriptions and assertions checking by using Wu's method is studied. We present an algorithm framework based on constructing polynomial data-flow model and calculating the characteristic sets of the polynomials. Our experiment shows that it is a new approach for assertion checking and can be taken as a useful theoretical insight for symbolic simulation based verification methodology.