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基于FPGA的虚拟逻辑分析仪研制开发

Release Time:2016-09-06  Hits:

Leading Scientist: 梁若冰

Project Participants: 赵亮

Project Source: 企事业单位委托科技项目

Status: 结题

Supported by: Beijing Institute of Technology

Nature of Project: 横向

Date of Project Approval: 2014-04-09

Scheduled Completion Time: 2015-12-14

Date of Project Initiation: 2014-05-22

Date of Project Completion: 2020-06-30

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