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基于FPGA的虚拟逻辑分析仪研制开发

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Leading Scientist:梁若冰

Project Participants:赵亮

Supported by:企事业单位委托科技项目

Status:结题

Supported by:北京理工大学

Nature of Project:横向

Date of Project Approval:2014-04-09

Scheduled completion time:2015-12-14

Date of Project Initiation:2014-05-22

Date of Project Completion:2020-06-30

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