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论文类型： 期刊论文

发表时间： 2011-02-01

发表刊物： JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS

收录刊物： SCIE、EI

卷号： 22

期号： 2

页面范围： 193-199

ISSN号： 0957-4522

摘要： Au-20 wt% Sn eutectic solder is used as bumps in flip chip package of power LED (Light Emitting Diode) due to its excellent properties. The Au/Sn dual-layer films were fabricated on Si wafer by pulse electroplating of Au and Sn sequentially, and the solid-solid interfacial reaction during aging and the eutectic reaction during reflow soldering were investigated in the present work. After storage at room temperature for 1 week, three phases of AuSn, AuSn2 and AuSn4 were sequentially formed at the Au/Sn (10 mu m/10 mu m) interface, and the thickness of this reaction region was about 5 mu m. Firstly, AuSn4 was formed at the Au/Sn interface, and then AuSn and AuSn2 were formed at the Au/AuSn4 interface. After aging at 150 A degrees C for 5 and 10 h, a similar layered structure of AuSn/AuSn2/AuSn4 was also observed. Due to the faster diffusion of Au to Sn layer, all the Sn elements were consumed after aging at 150 A degrees C for 15 h and AuSn4 layer gradually transformed into AuSn and AuSn2 layers. For the specimen of Au/Sn (9 mu m/6 mu m) films on Si chip, a bamboo-shoot-like microstructure of Au5Sn/AuSn/AuSn2 was formed in the reaction region after reflowed at 280 A degrees C for 10 s; while a typical two-phase (Au5Sn and AuSn) eutectic microstructure was formed after reflowed at 280 A degrees C for 60 s.