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论文类型：期刊论文

发表时间：2017-06-01

发表刊物：AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS

收录刊物：SCIE、EI、Scopus

卷号：76

页面范围：137-145

ISSN号：1434-8411

关键字：IEC61850-9-2 process bus; FPGA; Sampled values; IEEE 1588v2; Digital synchronization

摘要：In this paper, a network synchronization proposal for digital substation process bus in the process layer was designed. It appears differences of timing grouping queuing delay in the forward and backward on the channel due to the switch routing device, thus introducing queue-induced asymmetry, which is a major contributor to time offset and time delay between master and subordinate clocks. The sampled value of the transmission time error caused by the electronic transformer (ECT) signal processing channel and Ethernet communication channel is analyzed. An FPGA-based (field-programmable gate array, FPGA) digital synchronization approach for merging unit (MU) was proposed, which included oversampling, linear phase-shifting, dynamic interpolation resampling technique. It solved the sampled value message precise synchronization problems on the IEC61850-9-2 process bus. Time offset and delay were reduced more than 70 mu s between the master and subordinate clocks based on IEEE 1588v2, and he test results were well in 0.2 S level of IEC 60044 standard. Numerical examples are presented to demonstrate the effectiveness of the theoretical results. (C) 2017 Elsevier GmbH. All rights reserved.