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论文类型：期刊论文

发表时间：2014-08-23

发表刊物：Communications in Computer and Information Science

收录刊物：EI、Scopus

卷号：451 CCIS

页面范围：43-57

ISSN号：9783662444900

摘要：FPGA (Field-Programmable Gate Array) technology can provide excellent accuracy and efficiency for Chip verification, which has become the key bottleneck of SoC design. Due to the resource constraints of single FPGA chip, Multi-FPGA architecture was applied to the verification of the large scale SoC design. In recent years, a variety of Multi-FPGA verification platforms have been developed, but most of them indirectly part the SoC design on the Netlist level after the synthesis procedure. A partition method is proposed in this paper, which works directly on the RTL (Register Transfer Level) code. It presents a universal partition methodology with realistic and detailed implementation, applying a linear partition algorithm. The experiment simulation of leon3, a SoC design based on SPARC processor, runs at a speed of 8 MHz correctly, over 100,000 times faster than software simulation, 1-2 times of the BEE4 FPGA based recognizable platforms. © Springer-Verlag Berlin Heidelberg 2014.