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论文类型：会议论文

发表时间：2011-01-06

收录刊物：EI、CPCI-S、Scopus

卷号：48-49

页面范围：1227-1230

关键字：digital phase-locked loops; charge-pump; voltage-controlled oscillator; phase frequency detector

摘要：In this paper, the charge-pump PLL structure is well analyzed. By using top-down method, the digital PLL is designed from frequency phase detector, charge pump, loop filter, VCO to frequency divider. Based on 0.5 mu m CMOS mixed signal process, the schematic and layout design is finished on Cadence IC 5.1.4.1, and Hspice is used for the simulation. The layout verification and parasitic extraction is completed on industry mainstream Calibre software. Simulation results show that the digital PLL is with a 100MHz center frequency, the locking range is between 20MHz similar to 60MHz, the locking time is less than 1.5 mu s, and phase noise is -105dBc/Hz. The design has implemented the digital signal lock function and it can be used as an IP hard core in the clock recovery of communication systems and frequency synthesis of digital systems.