王开宇

个人信息Personal Information

教授级高工

硕士生导师

主要任职:控制科学与工程学院副院长

其他任职:大连理工大学电工电子国家级实验教学示范中心主任,大连理工大学电工电子国家级虚拟仿真实验教学中心主任

性别:男

毕业院校:德国卡尔斯普厄科技大学

学位:硕士

所在单位:控制科学与工程学院

学科:检测技术与自动化装置

办公地点:理工北门海山楼B1607

联系方式:QQ:1944765955

电子邮箱:wkaiyu@dlut.edu.cn

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Verilog HDL optimisation design and simulation for modified inversionless Berlerkamp-Massey algorithm and the multiplier over canonical field

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论文类型:期刊论文

发表时间:2013-01-01

发表刊物:International Journal of Mobile Network Design and Innovation

收录刊物:EI、Scopus

卷号:5

期号:1

页面范围:51-62

ISSN号:17442869

摘要:Reed-Solomon (RS) codes have been widely used in a variety of communication systems to protect digital transmission data against errors. This paper adopts the excellent inversionless Berlerkamp-Massey (IBM) algorithm as solving key equation algorithm for RS (204, 188) and then further modifies it to implement in less hardware resources after comparison with existing other algorithms. After that, we analyse critical path delay of the modified algorithm implemented in hardware and conclude that the multiplier over canonical field dominates a main part of the delay. Therefore, an efficient combinatorial multiplier of 4-input look up table (4-LUT) field programmable logic gate array (FPGA) is designed and then applied to the modified IBM algorithm. Results show that the modified IBM algorithm can be implemented using easier hardware structure, but when the proposed multiplier is applied to the modified IBM algorithm, in comparison with the two multipliers directly represented by a normal basis and matrix form, the speed to solve key equation increases by 10.2% and 18.4%, respectively. Copyright ? 2013 Inderscience Enterprises Ltd.