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Design and Performance Analysis of a Practical Load-Balanced Switch

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Indexed by:期刊论文

Date of Publication:2009-08-01

Journal:IEEE TRANSACTIONS ON COMMUNICATIONS

Included Journals:SCIE、EI、Scopus

Volume:57

Issue:8

Page Number:2420-2429

ISSN No.:0090-6778

Key Words:Load-balanced switches; throughput

Abstract:The load-balanced (LB) switch proposed by C.S. Chang et al. [1], [2] consists of two stages. First, a load-balancing stage converts arriving packets into uniform traffic. Then, a forwarding stage transfers packets from the linecards to their final output destination. Load-balanced switches do not need a centralized scheduler and can achieve 100% throughput or a broad class of traffic distributions. However, load-balanced switches may cause packets at the output port to be out of sequence. Several schemes have been proposed to tackle the out-of-sequence problem of the load-balanced switch. They are either too complex to implement, or introduce a large additional delay. In this paper, we present a practical load-balanced switch, called the Byte-Focal switch, which uses packet-by-packet scheduling to significantly improve the delay performance over switches of comparable complexity. We prove that the queues at the input need only finite buffering, and that the overall switch is stable under any traffic matrix. Our analysis shows that the average queuing delay is roughly linear with the switch size N, and although the worst case resequencing delay is N-2, the average resequencing delay is much smaller. This means that we can reduce the required resequencing buffer size significantly.

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