点击次数：

论文类型： 会议论文

发表时间： 2009-08-10

收录刊物： EI、CPCI-S、Scopus

页面范围： 802-805

摘要： LEDs (Light Emitting Diode) have a high potential to replace the conventional light bulb as the long-life, energy efficient, environmentally friendly and multi-use light source in the future. Using flip-chip (FC) technology, the thermal dissipation and luminescence efficiency of high-power LEDs can be improved. Therefore FC packaging also attracts great research interests for high brightness LEDs (HB-LED). However, solder bumping is a critical step in FC technology. In the present article an Au-30Sn (at.%) eutectic alloy bumping process developed for high-power LED flip-chip technology has been described. Au-Sn solder bumps can be manufactured by sequential non-cyanide electroplating of Au and Sn layers. This paper focuses on the formation of Au bumps and the optimization of electroplating parameters for pure Au. The quality of the Au layers and the deposition rates were studied in terms of electroplating temperature and sodium sulfite concentration in baths. A series of electroplated tests at different sodium sulfite concentrations ranging from 0.135 mol/L to 0.675 mol/L were performed in order to study the effect of sodium sulfite concentration on the quality and depositing rate of Au layers. After the optimization of the Au plating parameters, Au/Sn/Au triple-layer films for FC-LED bumps were fabricated.