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Indexed by:会议论文

Date of Publication:2017-04-16

Journal:7th International Conference on Information Science and Technology, ICIST 2017

Included Journals:Scopus、EI

Page Number:323-330

Abstract:The High Efficiency Video Coding (HEVC) standard, as the newest generation video coding standard issued in 2013, significantly improves compression performance relative to existing standards in about 50% bit-rate reduction for equal perceptual video quality with the cost of greatly increasing the computation complexity of the encoder/decoder. In order to improve the decoding efficiency, we design a set of parallel decoding algorithms based on the CPU+GPU heterogeneous platform for the HEVC decoder, in which, the reconstruction processes with high computation complexity, including the inverse quantization (IQ), the inverse discrete cosine transformation (IDCT), the intra/inter decoder, the de-blocking filter (DF), and the sample adaptive offset (SAO), are processed by GPU in parallel, while the network abstract layer (NAL) bit stream parsing and the CABAC bit stream decoding are processed by CPU using serial algorithms on account that they are not suitable for parallel implementation due to their internally contextual relevance. We implement the parallel algorithms by using the compute unified device architecture (CUDA) and test them with various video sequences. The experimental results show that our method can achieve a significant improvement on the computation efficiency for the whole decoding processes and can achieve real-Time decoding with more than 39 frames per second for HD videos. ? 2017 IEEE.