Indexed by:Conference Paper

Date of Publication:2011-08-20

Included Journals:Scopus、CPCI-S、EI

Volume:10

Issue:PART B

Page Number:1052-1058

Key Words:CMOS; current source; layout; layout simulation

Abstract:This paper presents a voltage threshold-based self-bias and can be used for integrated CMOS current. source structure. When the power supply voltage change from 3V to 6.5V. the current source can output 20 current constant currently and enable control terminal also be added that can effectively control the circuit open or closed. After pre - simulation achieve the desired effect we designed and verified the layout, then extracted the parasitic parameters and used it with the HSPICE software finish the layout simulation. The circuit can be good for the other sub-circuit modules to provide a stable DC bias, so that they can work in a suitable quiescent point. (C) 2011 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of Conference ESIAT2011 Organization Committee.