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Indexed by:期刊论文

Date of Publication:2014-10-01

Journal:Dongbei Daxue Xuebao/Journal of Northeastern University

Included Journals:EI、PKU、ISTIC、Scopus

Volume:35

Page Number:135-139

ISSN No.:10053026

Abstract:In order to reduce the development cycle of embedded system and improve the reusability of verification platform, a FPGA-based virtual verification framework on chip was proposed in this paper. By adding the virtual peripheral, a fully enclosed SoC verification platform was implemented on a single FPGA. With the use of virtualization peripheral interface, the platform could be configured dynamically, which could be applied to different embedded system. Meanwhile, the traditional Ethernet communication protocol was simplified and the asymmetric Gigabit Ethernet protocol was applied to interact with the host computer, which was convenient for H/W co-verification. In the experiments, the performance, configurability and reusability of the system were analyzed to verify the feasibility of the framework. ?, 2014, Northeastern University. All right reserved.