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论文类型：期刊论文

发表时间：2013-01-01

发表刊物：高电压技术

收录刊物：EI、PKU、ISTIC、CSCD、Scopus

卷号：39

期号：4

页面范围：797-804

ISSN号：1003-6520

摘要：A realization scheme of merging unit (MU) for electronic current transformers (ECT) and electronic voltage transformers (EVT) based on single field-programmable gate array (FPGA) and IEC 61850-9-2 protocol is given in this paper. The MU is divided into three modules: sampling pulse synchronization module, sampled values processing module and data frames transmission module. A two-stage synchronization scheme is proposed to compensate the data latency. In the first stage, the phase angle of the sampled signal is shifted forward in a large range by employing the digital phase-shifter. In the second stage, a fine adjustment for the signal phase angle is carried out in a small range by using the dynamic second-order Lagrange interpolation algorithm. This scheme can achieve SMV packet's highly accurate time synchronization in process bus. Tests about the basic bus data accuracy, performance of the temperature diversification and performance of the multi-channel signal in real-time communication show the testing is within the limits of the accuracy class 0.2 s in IEC 60044. The communication characteristics test proves the frame is fully comply with the format of IEC 61850-9-2. This series of tests demonstrate the utility and flexibility of the MU which can be applied in the digital substation based on IEC 61850.