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    • 教授     博士生导师 硕士生导师
    • 性别:男
    • 毕业院校:纽约理工大学
    • 学位:博士
    • 所在单位:计算机科学与技术学院
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    Design and Performance Analysis of a Practical Load-Balanced Switch

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      发布时间:2019-03-09

      论文类型:期刊论文

      发表时间:2009-08-01

      发表刊物:IEEE TRANSACTIONS ON COMMUNICATIONS

      收录刊物:Scopus、EI、SCIE

      卷号:57

      期号:8

      页面范围:2420-2429

      ISSN号:0090-6778

      关键字:Load-balanced switches; throughput

      摘要:The load-balanced (LB) switch proposed by C.S. Chang et al. [1], [2] consists of two stages. First, a load-balancing stage converts arriving packets into uniform traffic. Then, a forwarding stage transfers packets from the linecards to their final output destination. Load-balanced switches do not need a centralized scheduler and can achieve 100% throughput or a broad class of traffic distributions. However, load-balanced switches may cause packets at the output port to be out of sequence. Several schemes have been proposed to tackle the out-of-sequence problem of the load-balanced switch. They are either too complex to implement, or introduce a large additional delay. In this paper, we present a practical load-balanced switch, called the Byte-Focal switch, which uses packet-by-packet scheduling to significantly improve the delay performance over switches of comparable complexity. We prove that the queues at the input need only finite buffering, and that the overall switch is stable under any traffic matrix. Our analysis shows that the average queuing delay is roughly linear with the switch size N, and although the worst case resequencing delay is N-2, the average resequencing delay is much smaller. This means that we can reduce the required resequencing buffer size significantly.