点击次数：

论文类型： 会议论文

发表时间： 2018-01-01

收录刊物： CPCI-S

页面范围： 241-246

关键字： 3D IC; wafer-level hybrid bonding; insert Cu pillar solder bump; dry film adhesive; TSVs; reliability

摘要： Wafer-level hybrid bonding and through silicon vias (TSVs) are key technologies to fabricate 3D IC products with ultra-fine pitch bumps and high interconnects density. In this work, process optimization and reliability evaluation of 3D IC integration using wafer-level micro-bump/dry film adhesive hybrid bonding and via-last TSVs were presented. In order to obtain a well hybrid bonding interface, various hybrid bonding methods, i.e., low temperature bonding using no reflowed bump, high temperature bonding using no reflowed bump, and high temperature bonding using reflowed bump, were investigated. Key processes including dry film lamination, hybrid bonding, and via-last TSV fabrication were developed. Reliability of the hybrid bonded chips were characterized by various tests. The results indicate that wafer-level hybrid bonding with via-last TSVs approach is a reliable, simple solution to fabricate 3D IC products.