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论文类型：期刊论文

发表时间：2014-01-01

发表刊物：Sensors and Transducers

收录刊物：EI

卷号：171

期号：5

页面范围：86-92

摘要：Power SOI (Silicon-On-Insulator) devices have an inherent sandwich structure of MOS (Metal- Oxide-Semiconductor) gate which is very easy to suffer ESD (Electro-Static Discharge) overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor) were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design) platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.  © 2014 by IFSA Publishing, S. L.