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论文类型：会议论文

发表时间：2010-12-05

收录刊物：EI、Scopus

页面范围：1-5

摘要：A novel anti-ESD TGFPTD SOI LDMOS was proposed firstly for improve ESD robustness of TGFPTD SOI LDMOS in this paper. The proposed de vice was obtained by introducing an additional n+ implantation and rapid thermal annealing into the widen p-well region of conventional TGFPTD SOI LDMOS. 2D simulation of the proposed device upon a positive current pulse stimulus of HBM indicates that a hybrid conduction mechanism of Zener diodes, BJTs, SCR, resistors and capacitors exists during ESD period. Moreover, the gate voltage is clamped below 30% of the breakdown voltage of gate oxide and the induced gate charges are released in a very short time at about 1.0  s. Therefore, the proposed anti-ESD TGFPTD SOI LDMOS is featured of very high ESD robustness.*. ? 2010 IEEE.