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Indexed by:期刊论文

Date of Publication:2018-12-01

Journal:JOURNAL OF ELECTRONIC MATERIALS

Included Journals:SCIE、Scopus

Volume:47

Issue:12

Page Number:7544-7557

ISSN No.:0361-5235

Key Words:3D IC; micro-bump; B-stage adhesive film; wafer-level hybrid bonding; via-last TSVs

Abstract:Three-dimensional (3-D) small chip stacking using low cost wafer-level insert-bump hybrid bonding and via-last TSVs is proposed and investigated. The proposed hybrid bonding method realized by micro Cu pillar solder bumps and photo-patternable B-stage adhesive film has been successfully applied to an 8 inch wafer with 86 +/- 255 gross dies and a bump pitch of 150 mu m. The complete process flow is successfully validated and a well electrical connectivity for the whole wafer is obtained. Two hybrid bonding approaches, i.e., "adhesive-first" hybrid bonding and "Cu pillar bump-first" hybrid bonding, are studied. A void-free hybrid bonding interface with a final gap between top chip and bottom chip lower than 30 mu m is achieved using the "Cu pillar bump-first" hybrid bonding approach. The interaction of SnAg solder with electroless Ni-P/immersion Au and electro Ni are investigated. Two types of interfacial compounds, i.e., Ni3Sn4 and P-rich Ni layer containing Sn atoms, are found. The via-last through silicon vias (TSVs) have a diameter of 40 mu m and a depth of 95 mu m. The results indicate that it is a promising method for 3-D integrated circuits stacking technology using hybrid bonding and via-last TSVs.