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论文类型：期刊论文

发表时间：2012-08-01

发表刊物：Journal of Semiconductors

收录刊物：EI、ISTIC、Scopus

卷号：33

期号：8

ISSN号：16744926

摘要：A simplified compact model for a miniaturized cross-shaped CMOS integrated Hall device is presented. The model has a simple circuit structure, only consisting of a passive network with eight non-linear resistors and four current-controlled voltage sources. It completely considers the following effects: non-linear conductivity, geometry dependence of sensitivity, temperature drift, lateral diffusion, and junction field effect. The model has been implemented in Verilog-A hardware description language and was successfully performed in a Cadence Spectre simulator. The simulation results are in good accordance with the classic experimental results reported in the literature. ? 2012 Chinese Institute of Electronics.