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论文类型：会议论文

发表时间：2012-08-13

收录刊物：EI、CPCI-S、Scopus

页面范围：482-486

摘要：3D Integration is a good solution for extending Moore's momentum in the next decennium. Through Silicon Via (TSV) is an alternative interconnect technology for higher performance system integration with vertical stacking of chips in package. Due to high demands of chip miniaturization, small diameter TSV with high aspect ratio has become particularly important.
   This paper focuses on Cu electroplating via filling of small diameter, high aspect ratio TSV. Samples of different via diameters under various current densities are fabricated and analyzed in lab. In addition, exhaust and pre-wetting procedures are also introduced after a series of contrast experiments, robust copper filling result for small diameter (4 mu m similar to 6 mu m) TSVs with high aspect ratio up to 6:1 has been successfully realized. Based on the good copper filling result, a testing vehicle structure of 3D integration is fabricated.