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论文类型：期刊论文

发表时间：2017-01-01

发表刊物：IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY

收录刊物：SCIE、EI、Scopus

卷号：7

期号：1

页面范围：19-26

ISSN号：2156-3950

关键字：Cu/Sn/Cu interconnect; fine-pitch interconnect; solid-state-diffusion (SSD) bonding; wafer-level bonding

摘要：Low-temperature Cu/Sn/Cu solid-state-diffusion (SSD) bonding has been investigated in this paper. Twentymicrometer fine-pitch bumps with daisy-chain and Kelvin structures were fabricated by high-efficiency and low-cost electroplating process. Before bonding, the bump surface was treated with Ar( 5% H-2) plasma. Wafer-level bonding was performed with a pressure of 6.7 MPa at 200 degrees C for 60 min. Microstructure of the as-bonded interface consisted of five layers, i. e., Cu/Cu3Sn/Cu6Sn5/Cu3Sn/Cu, no Sn overflow was observed, and pure Sn was completely consumed during bonding process. After annealing at 200 degrees C for 60 min under N-2 atmosphere, Cu6Sn5 was exhausted, and the average shear strength increased to 11.4 MPa. The resistance measurements were approximate to the theoretical estimation. The bonded performance had no significant change after thermal cycling test. The bonding interface exhibited an expected antielectromigration capability. It is concluded that Cu/Sn/Cu SSD bonding would be one of the potential technologies for 3-D integration.