Release Time:2019-03-11  Hits:

Indexed by: Journal Article

Date of Publication: 2004-12-01

Journal: Journal of Information and Computational Science

Included Journals: EI、Scopus

Volume: 1

Issue: 3

Page Number: 341-345

ISSN: 15487741

Key Words: Cache memory; Parameter estimation; Real time systems; Scheduling, Cache conflict graph; Embedded software; Modern microprocessor; Motorola MMC2107; Performance simulation; TCP pacing end to end congestion control algorithm; Worst case execution time (WCET), Embedded systems

Abstract: It is necessary to compute the execution time upper bound of embedded hard real-time program under the worst condition in embedded system design, which decides how hardware and software to partition and how to schedule process. Modern microprocessor which use cache memory system and instruction pre-fetching increase the difficulty to compute the upper bound accurately. A new estimation method of embedded software performance based on instruction cache and pre-fetching model is proposed, which use control flow graph and cache conflict graph and combine instruction pre-fetching into cache analysis, it makes the execution time upper bound more accurate. This paper propose an improved TCP pacing end-to-end congestion control algorithm to solve existing issues.