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论文类型：会议论文

发表时间：2012-12-13

收录刊物：EI、CPCI-S、Scopus

摘要：3D integration is one of the potential solutions for extending Moore's momentum in the next decennium. Through silicon via (TSV) is a key interconnect technology for future's higher performance and system integration with vertical stacked chips in package, which can achieve smaller interconnection delay, heterogeneous technologies integration and potentially lower cost and reduce time-to-market.
   In this paper, a testing vehicle of 3D stacking dies with TSVs as the major interconnect was designed. A dummy die with 5 mu m diameter TSVs was fabricated and assembled on a silicon interposer, which has TSVs as well. The dummy die/chip was bonded on the interposer through Cu-Sn-Cu bonding at 280 degrees C, and then, the bonded module was assembled on designed testing board.